VROR.VV

Vector Rotate Right

VROR.VV vd, vs2, vs1, vm

Rotates bits in elements of vs2 right by amounts in vs1.

Encoding

Binary Layout

010100

31:26

vm

25

vs2

24:20

vs1

19:15

000

14:12

vd

11:7

1010111

6:0

 

Format OPIVV

Opcode 0x50000057

Extension Zvbb

Operands

• vd
  Destination vector register
• vs2
  Source vector register 2
• vs1
  Source vector register 1

Example

VROR.VV v1, v4, v2, v0.t

Related

More in Zvbb

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Rotates each vector element right by the corresponding shift amount.

Operation

foreach(i < vl): vd[i] = (vs2[i] >> vs1[i]) | (vs2[i] << (SEW - vs1[i]));