VMV4R.V

Vector Move 4 Registers (Whole)

VMV4R.V vd, vs2

Moves 4 consecutive vector registers, ignoring VL and VTYPE.

Encoding

Binary Layout

1001111

31:25

vs2

24:20

00011011

19:12

vd

11:7

1010111

6:0

 

Format OPVI

Opcode 0x9E01B057

Extension V

Operands

• vd
  Dest Group
• vs2
  Source Group

Example

VMV4R.V v1, v4

Related

More in V

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Copies 4 vector register(s) from vs2 to vd, independent of vtype or vl. No masking.

Operation

vd[0:3] = vs2[0:3];