VMUL.VV

Vector Integer Multiply

VMUL.VV vd, vs2, vs1, vm

Multiplies elements of two vector registers.

Details

Performs element-wise integer multiplication (low bits) on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.

Pseudocode Operation

foreach(i < vl): vd[i] = vs1[i] * vs2[i];

Example

VMUL.VV v10, v8, v9

Encoding

Binary Layout
100101
31:26
vm
25
vs2
24:20
vs1
19:15
010
14:12
vd
11:7
1010111
6:0
 
Format OPIVV
Opcode 0x57
Extension V

Operands

  • vd
    Destination vector register
  • vs2
    Source vector register 2
  • vs1
    Source vector register 1