VFDIV.VV

Vector Float Divide

VFDIV.VV vd, vs2, vs1, vm

Divides elements of two floating-point vectors.

Encoding

Binary Layout

100000

31:26

vm

25

vs2

24:20

vs1

19:15

001

14:12

vd

11:7

1010111

6:0

 

Format OPFVV

Opcode 0x80001057

Extension V

Operands

• vd
  Destination vector register
• vs2
  Divisor
• vs1
  Dividend

Example

VFDIV.VV v1, v4, v2, v0.t

Related

More in V

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Performs element-wise floating-point division on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.

Operation

foreach(i < vl): vd[i] = vs1[i] / vs2[i];