VDIVU.VV

Vector Integer Divide Unsigned

VDIVU.VV vd, vs2, vs1, vm

Divides unsigned vector elements.

Details

Performs element-wise unsigned integer division on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.

Pseudocode Operation

foreach(i < vl): vd[i] = vs1[i] /u vs2[i];

Example

VDIVU.VV v1, v4, v2, v0.t

Encoding

Binary Layout
100000
31:26
vm
25
vs2
24:20
vs1
19:15
000
14:12
vd
11:7
1010111
6:0
 
Format OPIVV
Opcode 0x57
Extension V

Operands

  • vd
    Destination vector register
  • vs2
    Divisor
  • vs1
    Dividend