VFADD.VV

Vector Float Add

VFADD.VV vd, vs2, vs1, vm

Adds elements of two vector registers (Floating Point).

Details

Performs element-wise floating-point addition on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.

Pseudocode Operation

foreach(i < vl): vd[i] = vs1[i] + vs2[i];

Example

VFADD.VV v1, v4, v2, v0.t

Encoding

Binary Layout
000000
31:26
vm
25
vs2
24:20
vs1
19:15
001
14:12
vd
11:7
1010111
6:0
 
Format OPFVV
Opcode 0x57
Extension V

Operands

  • vd
    Destination vector register
  • vs2
    Source vector register 2
  • vs1
    Source vector register 1