VAESEM.VV

Vector AES Encryption Middle Round

VAESEM.VV vd, vs2, vs1

Performs a middle AES encryption round.

Encoding

Binary Layout

1010001

31:25

vs2

24:20

00010010

19:12

vd

11:7

1110111

6:0

 

Format OPIVV

Opcode 0xA2012077

Extension Zvkned

Operands

• vd
  State
• vs2
  Round Key
• vs1
  Undef

Example

VAESEM.VV v1, v4, v2

Related

More in Zvkned

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Performs a vectorised AES cryptographic round operation. Each element group undergoes one step of the cipher algorithm in parallel. See the Zvk vector crypto extension for full semantic details.

Operation

vd = AES_Encrypt_Middle(vd, vs2);