VANDN.VV

Vector Bitwise AND-NOT

VANDN.VV vd, vs2, vs1, vm

Computes vd = vs2 & ~vs1 (bitwise AND with inverted source).

Details

Performs element-wise AND with inverted source (vs2 op ~vs1), writing results to vd.

Pseudocode Operation

foreach(i < vl): vd[i] = vs2[i] & ~vs1[i];

Example

VANDN.VV v1, v4, v2, v0.t

Encoding

Binary Layout
000001
31:26
vm
25
vs2
24:20
vs1
19:15
000
14:12
vd
11:7
1010111
6:0
 
Format OPIVV
Opcode 0x57
Extension Zvbb

Operands

  • vd
    Destination vector register
  • vs2
    Source vector register 2
  • vs1
    Source vector register 1