DIVW

Divide Word

DIVW rd, rs1, rs2

Performs 32-bit signed division of rs1 by rs2, sign-extending the result.

Details

DIVW performs signed 32-bit division of the lower 32 bits of rs1 by rs2, sign-extends the quotient to 64 bits, and writes to rd (RV64 only). Division by zero yields −1.

Pseudocode Operation

R[rd] = sext(R[rs1][31:0] /s R[rs2][31:0]);

Example

DIVW x10, x11, x12

Encoding

Binary Layout
0000001
31:25
rs2
24:20
rs1
19:15
100
14:12
rd
11:7
0111011
6:0
 
Format R-Type
Opcode 0x3B
Extension M

Operands

  • rd
    Quotient
  • rs1
    Dividend
  • rs2
    Divisor