REMW

Remainder Word

REMW rd, rs1, rs2

Computes the remainder of 32-bit signed division, sign-extending the result.

Encoding

Binary Layout

0000001

31:25

rs2

24:20

rs1

19:15

110

14:12

rd

11:7

0111011

6:0

 

Format R-Type

Opcode 0x0200603B

Extension M

Operands

• rd
  Remainder
• rs1
  Dividend
• rs2
  Divisor

Example

REMW x10, x11, x12

// 32-bit signed remainder.

Related

More in M

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

REMW computes the signed 32-bit remainder of rs1 ÷ rs2, sign-extends to 64 bits, and writes to rd (RV64 only).

Operation

R[rd] = sext(R[rs1][31:0] %s R[rs2][31:0]);