ADDW

Add Word

ADDW rd, rs1, rs2

Adds two 32-bit registers and sign-extends the result to 64 bits.

Encoding

Binary Layout

0000000

31:25

rs2

24:20

rs1

19:15

000

14:12

rd

11:7

0111011

6:0

 

Format R-Type

Opcode 0x0000003B

Extension RV64I

Operands

• rd
  Destination Register
• rs1
  Source Register 1
• rs2
  Source Register 2

Example

ADDW x10, x11, x12

// Performs 32-bit addition of x11 and x12, result is sign-extended to 64 bits.

Related

More in RV64I

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

ADDW adds rs1 and rs2, truncates the result to 32 bits, sign-extends to 64 bits, and writes to rd. Arithmetic overflow is ignored.

Operation

R[rd] = sext((R[rs1] + R[rs2])[31:0]);