VWREDSUM.VS

Vector Widening Reduction Sum Signed

VWREDSUM.VS vd, vs2, vs1, vm

Sums N-bit elements into a 2*N-bit scalar accumulator (Signed).

Encoding

Binary Layout

110001

31:26

vm

25

vs2

24:20

vs1

19:15

000

14:12

vd

11:7

1010111

6:0

 

Format OPMVV

Opcode 0xC4000057

Extension V

Operands

• vd
  Dest (Scalar Wide)
• vs2
  Vector (Narrow)
• vs1
  Start (Wide)

Example

VWREDSUM.VS v1, v4, v2, v0.t

Related

More in V

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.

Operation

vd[0] = vs1[0] + sum(extend(vs2[*]));