VFWADD.VV

Vector Widening Float Add

VFWADD.VV vd, vs2, vs1, vm

Adds N-bit floats to produce 2*N-bit float results (e.g., FP16 + FP16 -> FP32).

Details

Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.

Pseudocode Operation

foreach(i < vl): vd[i] = extend(vs1[i]) + extend(vs2[i]);

Example

VFWADD.VV v1, v4, v2, v0.t

Encoding

Binary Layout
110000
31:26
vm
25
vs2
24:20
vs1
19:15
001
14:12
vd
11:7
1010111
6:0
 
Format OPFVV
Opcode 0x57
Extension V

Operands

  • vd
    Dest (2*SEW)
  • vs2
    Src 2 (SEW)
  • vs1
    Src 1 (SEW)