DIVU

Divide Unsigned

DIVU rd, rs1, rs2

Performs unsigned integer division.

Encoding

Binary Layout

0000001

31:25

rs2

24:20

rs1

19:15

101

14:12

rd

11:7

0110011

6:0

 

Format R-Type

Opcode 0x02005033

Extension M

Operands

• rd
  Destination register (integer)
• rs1
  Dividend
• rs2
  Divisor

Example

DIVU x5, x6, x7

// Unsigned division.

Related

Across architectures

Integer Divide : how x86, ARM, RISC-V, and PowerISA each do this.

More in M

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

DIVU divides rs1 by rs2 using unsigned division and writes the quotient to rd, truncated toward zero. Division by zero yields 2^XLEN - 1.

Operation

R[rd] = R[rs1] /u R[rs2];