ANDI
Logical AND Immediate
ANDI rd, rs1, imm
Performs a bitwise logical AND between a register and a sign-extended 12-bit immediate.
Encoding
Binary Layout
imm12
31:20
rs1
19:15
111
14:12
rd
11:7
0010011
6:0
Operands
-
rd
Destination Register -
rs1
Source Register -
imm
12-bit Signed Immediate
Example
ANDI x10, x11, 15
// Keeps only the lowest 4 bits of x11 (mask 0xF).
Related
More in RV32I
Reference
View in RISC-V Unprivileged ISA Specification ↗
RISC-V ISA Manual
Description
ANDI performs a bitwise AND of register rs1 with the sign-extended 12-bit immediate, writing the result to rd.
Operation
R[rd] = R[rs1] & sext(imm);