AND

Logical AND

AND rd, rs1, rs2

Performs a bitwise logical AND operation between two registers.

Encoding

Binary Layout

0000000

31:25

rs2

24:20

rs1

19:15

111

14:12

rd

11:7

0110011

6:0

 

Format R-Type

Opcode 0x00007033

Extension RV32I

Operands

• rd
  Destination Register
• rs1
  Source Register 1
• rs2
  Source Register 2

Example

AND x10, x11, x12

// Bitwise AND of x11 and x12.

Related

More in RV32I

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

AND performs a bitwise logical AND of the values in rs1 and rs2, writing the result to rd.

Operation

R[rd] = R[rs1] & R[rs2];