C.ADDW

Compressed Add Word

C.ADDW rd', rs2'

Adds two registers (32-bit result sign-extended, RV64).

Details

Adds rd and rs2 (16-bit), sign-extends the 32-bit result to 64 bits (RV64/RV128 only).

Pseudocode Operation

R[rd'] = sext((R[rd'] + R[rs2'])[31:0]);

Example

C.ADDW rd', rs2'

Encoding

Binary Layout
?
31:16
100111
15:10
rd_rs1_p
9:7
01
6:5
rs2_p
4:2
01
1:0
 
Format CA
Opcode 0x00009C21
Extension C

Operands

  • rd'
    Dest/Src1
  • rs2'
    Source register 2 (3-bit compressed)