AES64ES
AES-64 Encryption Schedule
AES64ES rd, rs1, rs2
Performs one round of AES-128 encryption key schedule generation.
Encoding
Binary Layout
0011001
31:25
rs2
24:20
rs1
19:15
000
14:12
rd
11:7
0110011
6:0
Operands
-
rd
Destination register (integer) -
rs1
Source register 1 (integer) -
rs2
Source register 2 (integer)
Example
AES64ES x10, x11, x12
// AES Key Gen.
Related
More in Zkne
Reference
View in RISC-V Unprivileged ISA Specification ↗
RISC-V ISA Manual
Description
AES64ES performs two phases of the AES forward SubBytes and ShiftRows transformation. Used in AES encryption.
Operation
R[rd] = aes_encrypt_schedule(R[rs1], R[rs2]);