FNMADD.H

Float Negated Fused Multiply-Add (Half)

FNMADD.H rd, rs1, rs2, rs3

Computes -(rs1 * rs2) - rs3 with single rounding (16-bit).

Details

Performs half-precision (16-bit) floating-point fused negate-multiply-add. The operation computes fused negate-multiply-add on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.

Pseudocode Operation

F[rd] = -((F[rs1] * F[rs2]) + F[rs3]);

Example

FNMADD.H t0, a0, a1, a2

Encoding

Binary Layout
rs3
31:27
00
26:25
rs2
24:20
rs1
19:15
rm
rd
14:10
1001111
9:3
 
Format R4-Type
Opcode 0x4F
Extension Zfh

Operands

  • rd
    Destination register (integer)
  • rs1
    Source register 1 (integer)
  • rs2
    Source register 2 (integer)
  • rs3
    Src 3