C.AND

Compressed AND

C.AND rd', rs2'

Bitwise AND of two registers.

Encoding

Binary Layout

?

31:16

100011

15:10

rd_rs1_p

9:7

11

6:5

rs2_p

4:2

01

1:0

 

Format CA

Opcode 0x00008C61

Extension C

Operands

• rd'
  Dest/Src1
• rs2'
  Source register 2 (3-bit compressed)

Example

C.AND x8, x9

// x8 = x8 & x9

Related

More in C

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Computes the bitwise AND of rd′ and rs2′, writing the result to rd′.

Operation

R[rd'] = R[rd'] & R[rs2'];