C Instructions
42 RISC-V instructions in this extension - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| C.ADD | C.ADD rd, rs2 | CR | Adds two registers. |
| C.ADDI | C.ADDI rd, imm | CI | Adds a non-zero immediate to a register. |
| C.ADDI16SP | C.ADDI16SP imm | CI | Adds a signed non-zero immediate to the stack pointer (x2). |
| C.ADDI4SPN | C.ADDI4SPN rd', uimm | CIW | Adds a zero-extended non-zero immediate to the stack pointer (x2) and stores the result in a register. |
| C.ADDIW | C.ADDIW rd, imm | CI | Adds a signed immediate to a register (32-bit result sign-extended, RV64). |
| C.ADDW | C.ADDW rd', rs2' | CA | Adds two registers (32-bit result sign-extended, RV64). |
| C.AND | C.AND rd', rs2' | CA | Bitwise AND of two registers. |
| C.ANDI | C.ANDI rd', imm | CB | Computes bitwise AND with a signed immediate. |
| C.BEQZ | C.BEQZ rs1', offset | CB | Branches if the register is zero. |
| C.BNEZ | C.BNEZ rs1', offset | CB | Branches if the register is not zero. |
| C.EBREAK | C.EBREAK | CR | Triggers a debugger breakpoint. |
| C.FLD | C.FLD rd', offset(rs1') | CL | Loads a double-precision float from memory (Compressed). |
| C.FLDSP | C.FLDSP rd, offset(x2) | CI | Loads a double-precision float from the stack pointer. |
| C.FLW | C.FLW rd', offset(rs1') | CL | Loads a single-precision float from memory (Compressed). |
| C.FLWSP | C.FLWSP rd, offset(x2) | CI | Loads a single-precision float from the stack pointer. |
| C.FSD | C.FSD rs2', offset(rs1') | CS | Stores a double-precision float to memory (Compressed). |
| C.FSDSP | C.FSDSP rs2, offset(x2) | CSS | Stores a double-precision float to the stack pointer. |
| C.FSW | C.FSW rs2', offset(rs1') | CS | Stores a single-precision float to memory (Compressed). |
| C.FSWSP | C.FSWSP rs2, offset(x2) | CSS | Stores a single-precision float to the stack pointer. |
| C.J | C.J offset | CJ | Unconditional PC-relative jump. |
| C.JAL | C.JAL offset | CJ | Performs a PC-relative jump and stores return address in x1 (ra). RV32 only. |
| C.JALR | C.JALR rs1 | CR | Jumps to register address and links (saves PC+2 to ra). |
| C.JR | C.JR rs1 | CR | Unconditionally jumps to address in register. |
| C.LD | C.LD rd', offset(rs1') | CL | Loads a 64-bit value from memory (Compressed, RV64). |
| C.LDSP | C.LDSP rd, offset(x2) | CI | Loads a 64-bit value from the stack pointer (RV64). |
| C.LI | C.LI rd, imm | CI | Loads a 6-bit signed immediate into a register. |
| C.LUI | C.LUI rd, imm | CI | Loads a non-zero 6-bit immediate into bits 17-12 of the destination register, clears lower 12 bits, sign-extends bit 17. |
| C.LW | C.LW rd', offset(rs1') | CL | Loads a 32-bit word from memory using a compressed encoding. |
| C.LWSP | C.LWSP rd, offset(x2) | CI | Loads a word from the stack pointer (x2). |
| C.MV | C.MV rd, rs2 | CR | Copies register rs2 to rd. |
| C.NOP | C.NOP | CI | Performs no operation (Compressed encoding). |
| C.OR | C.OR rd', rs2' | CA | Bitwise OR of two registers. |
| C.SD | C.SD rs2', offset(rs1') | CS | Stores a 64-bit value to memory (Compressed, RV64). |
| C.SDSP | C.SDSP rs2, offset(x2) | CSS | Stores a 64-bit value to the stack pointer (RV64). |
| C.SLLI | C.SLLI rd, imm | CI | Logically shifts a register left by immediate. |
| C.SRAI | C.SRAI rd', imm | CB | Arithmetically shifts a register right by immediate. |
| C.SRLI | C.SRLI rd', imm | CB | Logically shifts a register right by immediate. |
| C.SUB | C.SUB rd', rs2' | CA | Subtracts two registers. |
| C.SUBW | C.SUBW rd', rs2' | CA | Subtracts two registers (32-bit result sign-extended, RV64). |
| C.SW | C.SW rs2', offset(rs1') | CS | Stores a 32-bit word to memory using a compressed encoding. |
| C.SWSP | C.SWSP rs2, offset(x2) | CSS | Stores a word to the stack pointer (x2). |
| C.XOR | C.XOR rd', rs2' | CA | Bitwise XOR of two registers. |