VLSEG3E8.V

Vector Load Segment (3 fields, 8-bit)

VLSEG3E8.V vd, (rs1), vm

Loads 3 fields (e.g., RGB) of 8-bit elements into 3 vector registers.

Encoding

Binary Layout

010000

31:26

vm

25

00000

24:20

rs1

19:15

000

14:12

vd

11:7

0000111

6:0

 

Format VL-Type

Opcode 0x40000007

Extension V

Operands

• vd
  Dest Group (3 regs)
• rs1
  Base Addr

Example

VLSEG3E8.V v1, a0, v0.t

Related

More in V

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Performs a vector strided load of 3-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.

Operation

Load 3 interleaved 8-bit streams into 3 vector registers.