VSLL.VI
Vector Shift Left Logical Immediate
VSLL.VI vd, vs2, imm, vm
Shifts elements left by immediate.
Encoding
Binary Layout
100101
31:26
vm
25
vs2
24:20
zimm5
19:15
011
14:12
vd
11:7
1010111
6:0
Operands
-
vd
Destination vector register -
vs2
Source vector register 2 -
imm
Signed immediate value
Example
VSLL.VI v1, v4, 16, v0.t
Related
More in V
Reference
View in RISC-V Unprivileged ISA Specification ↗
RISC-V ISA Manual
Description
Performs element-wise left logical shift on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.
Operation
vd = vs2 << imm;