VLSEG4E8.V

Vector Load Segment (4 fields, 8-bit)

VLSEG4E8.V vd, (rs1), vm

Loads 4 fields (e.g., RGBA) of 8-bit elements into 4 vector registers.

Details

Performs a vector strided load of 4-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.

Pseudocode Operation

Load 4 interleaved 8-bit streams into 4 vector registers.

Example

VLSEG4E8.V v1, a0, v0.t

Encoding

Binary Layout
000110
31:26
00111
25:21
vm
20
rs1
19:15
000
14:12
vd
11:7
0000111
6:0
 
Format VL-Type
Opcode 0x07
Extension V

Operands

  • vd
    Dest Group (4 regs)
  • rs1
    Base Addr