VLSE32.V

Vector Load Strided Element (32-bit)

VLSE32.V vd, (rs1), rs2, vm

Loads elements from memory with a fixed stride.

Details

Performs a vector strided load of 32-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.

Pseudocode Operation

foreach(i < vl): vd[i] = M[rs1 + i * rs2];

Example

VLSE32.V v1, a0, a1, v0.t

Encoding

Binary Layout
000110
31:26
mop
vm
25
rs1
24:20
110
19:17
vd
16:12
0000111
11:5
 
Format VL-Type
Opcode 0x07
Extension V

Operands

  • vd
    Vector Dest
  • rs1
    Base Address
  • rs2
    Stride