ADDIW
Add Immediate Word
ADDIW rd, rs1, imm
Adds a 12-bit immediate to a register (32-bit arithmetic) and sign-extends to 64 bits.
Encoding
Binary Layout
imm12
31:20
rs1
19:15
000
14:12
rd
11:7
0011011
6:0
Operands
-
rd
Destination Register -
rs1
Source Register -
imm
12-bit Signed Immediate
Example
ADDIW x5, x6, 5
// Adds 5 to lower 32 bits of x6, sign-extends result to x5.
Related
More in RV64I
Reference
View in RISC-V Unprivileged ISA Specification ↗
RISC-V ISA Manual
Description
ADDIW adds the sign-extended 12-bit immediate to rs1, truncates to 32 bits, sign-extends to 64 bits, and writes to rd. Arithmetic overflow is ignored.
Operation
R[rd] = sext((R[rs1] + sext(imm))[31:0]);