VMSLTU.VV

Vector Mask Set Less Than (Unsigned)

VMSLTU.VV vd, vs2, vs1, vm

Sets destination mask bit if vs2 < vs1 (unsigned).

Encoding

Binary Layout

011010

31:26

vm

25

vs2

24:20

vs1

19:15

000

14:12

vd

11:7

1010111

6:0

 

Format OPIVV

Opcode 0x68000057

Extension V

Operands

• vd
  Dest Mask
• vs2
  Source vector register 2
• vs1
  Source vector register 1

Example

VMSLTU.VV v1, v4, v2, v0.t

Related

More in V

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Compares elements element-wise for less than and writes a mask result to vd.

Operation

foreach(i < vl): vd[i] = (vs2[i] <u vs1[i]) ? 1 : 0;