VMSLT.VI

Vector Mask Set Less Than Immediate

VMSLT.VI vd, vs2, imm, vm

Sets mask if element < imm (Signed).

Encoding

Binary Layout

011011

31:26

vm

25

vs2

24:20

imm

011

19:17

vd

16:12

1010111

11:5

 

Format OPIVI

Opcode 0x74003057

Extension V

Operands

• vd
  Mask
• vs2
  Source vector register 2
• imm
  Val

Example

VMSLT.VI v1, v4, 16, v0.t

Related

More in V

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Compares elements element-wise for less than and writes a mask result to vd.

Operation

vd = (vs2 < imm);