Pseudo Instructions
20 RISC-V instructions in this extension - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| BEQZ | BEQZ rs, offset | B-Type | Branches if the register is zero. |
| BNEZ | BNEZ rs, offset | B-Type | Branches if the register is not zero. |
| CALL | CALL symbol | Pseudo | Calls a function by jumping to an address and saving the return address. |
| CSRC | CSRC csr, rs | I-Type | Clears bits in a CSR (bitwise AND NOT). |
| CSRR | CSRR rd, csr | I-Type | Reads the value of a CSR into a register. |
| CSRS | CSRS csr, rs | I-Type | Sets bits in a CSR (bitwise OR). |
| CSRW | CSRW csr, rs | I-Type | Writes a register value to a CSR. |
| J | J offset | J-Type | Unconditionally jumps to a target offset. |
| JR | JR rs | I-Type | Unconditionally jumps to an address held in a register. |
| LI | LI rd, imm | U-Type | Loads an arbitrary immediate value into a register. |
| MV | MV rd, rs | I-Type | Copies the value of one register into another. |
| NEG | NEG rd, rs | R-Type | Computes the two's complement negation (arithmetic negative). |
| NOP | NOP | I-Type | Performs no operation. Used for alignment or timing delays. |
| NOT | NOT rd, rs | I-Type | Computes the bitwise logical negation (one's complement). |
| RDCYCLE | RDCYCLE rd | I-Type | Reads the lower 32/64 bits of the cycle counter. |
| RDINSTRET | RDINSTRET rd | I-Type | Reads the count of instructions retired (completed). |
| RDTIME | RDTIME rd | I-Type | Reads the lower 32/64 bits of the real-time clock. |
| RET | RET | I-Type | Returns from a subroutine call. |
| SEQZ | SEQZ rd, rs | I-Type | Sets rd to 1 if rs is zero, otherwise 0. |
| SNEZ | SNEZ rd, rs | R-Type | Sets rd to 1 if rs is not zero, otherwise 0. |