V Instructions
171 RISC-V instructions in this extension - showing 71 per page, page 2 of 2 - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| VMV2R.V | VMV2R.V vd, vs2 | OPVI | Moves 2 consecutive vector registers, ignoring VL and VTYPE. |
| VMV4R.V | VMV4R.V vd, vs2 | OPVI | Moves 4 consecutive vector registers, ignoring VL and VTYPE. |
| VMV8R.V | VMV8R.V vd, vs2 | OPVI | Moves 8 consecutive vector registers, ignoring VL and VTYPE. |
| VMXNOR.MM | VMXNOR.MM vd, vs2, vs1 | OPMVV | Computes vd = ~(vs1 ^ vs2) (mask operation). |
| VNCLIP.WV | VNCLIP.WV vd, vs2, vs1, vm | OPIVV | Shifts elements right, rounds, and clips (saturates) the result to the destination width. Critical for Quantization. |
| VNCLIPU.WI | VNCLIPU.WI vd, vs2, imm, vm | OPIVI | Shifts right (logical), rounds, and clips to unsigned destination. Used for pixel packing. |
| VNMSUB.VV | VNMSUB.VV vd, vs1, vs2, vm | OPIVV | Computes vd = -(vd - (vs1 * vs2)). |
| VNSRA.WI | VNSRA.WI vd, vs2, imm, vm | OPIVI | Shifts wide elements right (arithmetic) by immediate and narrows. |
| VNSRA.WX | VNSRA.WX vd, vs2, rs1, vm | OPIVX | Arithmetically shifts 2*N-bit elements right and narrows to N-bits. |
| VNSRL.WI | VNSRL.WI vd, vs2, imm, vm | OPIVI | Shifts wide elements right by immediate and narrows. |
| VNSRL.WX | VNSRL.WX vd, vs2, rs1, vm | OPIVX | Shifts 2*N-bit elements right and narrows the result to N-bits. |
| VOR.VI | VOR.VI vd, vs2, imm, vm | OPIVI | Bitwise OR with immediate. |
| VOR.VV | VOR.VV vd, vs2, vs1, vm | OPIVV | Performs bitwise OR on elements of two vectors. |
| VREDAND.VS | VREDAND.VS vd, vs2, vs1, vm | OPMVV | Reduces a vector to a scalar using bitwise AND. |
| VREDMAX.VS | VREDMAX.VS vd, vs2, vs1, vm | OPMVV | Reduces a vector to a scalar by finding the maximum signed element. |
| VREDMIN.VS | VREDMIN.VS vd, vs2, vs1, vm | OPMVV | Reduces a vector to a scalar by finding the minimum signed element. |
| VREDOR.VS | VREDOR.VS vd, vs2, vs1, vm | OPMVV | Reduces a vector to a scalar using bitwise OR. |
| VREDSUM.VS | VREDSUM.VS vd, vs2, vs1, vm | OPMVV | Reduces a vector to a scalar by summing all elements. |
| VREM.VV | VREM.VV vd, vs2, vs1, vm | OPIVV | Computes signed remainder. |
| VREMU.VV | VREMU.VV vd, vs2, vs1, vm | OPIVV | Computes unsigned remainder. |
| VRGATHER.VI | VRGATHER.VI vd, vs2, imm, vm | OPIVI | Gathers element at index 'imm' from vs2 (splat). |
| VRGATHER.VV | VRGATHER.VV vd, vs2, vs1, vm | OPIVV | Gathers elements from a vector register using indices from another vector register. |
| VRSUB.VI | VRSUB.VI vd, vs2, imm, vm | OPIVI | Computes vd = imm - vs2. |
| VRSUB.VX | VRSUB.VX vd, vs2, rs1, vm | OPIVX | Subtracts vector elements from a scalar value (scalar - vector). |
| VSADD.VV | VSADD.VV vd, vs2, vs1, vm | OPIVV | Adds elements with signed saturation (clips to Max/Min instead of wrapping). |
| VSADDU.VV | VSADDU.VV vd, vs2, vs1, vm | OPIVV | Adds unsigned integers with saturation (clips to max instead of wrapping). |
| VSBC.VVM | VSBC.VVM vd, vs2, vs1, v0 | OPIVV | Subtracts two vectors minus a borrow-in from the mask register. |
| VSE16.V | VSE16.V vs3, (rs1), vm | VS-Type | Stores a vector of 16-bit elements to memory. |
| VSE32.V | VSE32.V vs3, (rs1), vm | V-Store | Stores a vector of 32-bit elements from a vector register to memory. |
| VSE64.V | VSE64.V vs3, (rs1), vm | VS-Type | Stores a vector of 64-bit elements to memory. |
| VSE8.V | VSE8.V vs3, (rs1), vm | VS-Type | Stores a vector of 8-bit elements to memory. |
| VSETIVLI | VSETIVLI rd, uimm, vtypei | V-Type | Sets vector length (VL) and type (VTYPE) using a 5-bit immediate for the requested length. |
| VSETVL | VSETVL rd, rs1, rs2 | V-Type | Sets the vector length (VL) based on the application vector length (AVL) in rs1 and configuration in rs2. |
| VSETVLI | VSETVLI rd, rs1, vtypei | V-Type | Configures the vector length (vl) and vector type (vtype) based on application needs. |
| VSLIDE1DOWN.VX | VSLIDE1DOWN.VX vd, vs2, rs1, vm | OPIVX | Moves elements down by 1, injecting scalar into top index. |
| VSLIDE1UP.VX | VSLIDE1UP.VX vd, vs2, rs1, vm | OPIVX | Moves elements up by 1, injecting scalar into index 0. |
| VSLIDEDOWN.VI | VSLIDEDOWN.VI vd, vs2, imm, vm | OPIVI | Moves elements down by immediate amount. |
| VSLIDEDOWN.VX | VSLIDEDOWN.VX vd, vs2, rs1, vm | OPIVX | Moves elements down by a scalar amount (vd[i] = vs2[i + rs1]). |
| VSLIDEUP.VI | VSLIDEUP.VI vd, vs2, imm, vm | OPIVI | Moves elements up by immediate amount. |
| VSLIDEUP.VX | VSLIDEUP.VX vd, vs2, rs1, vm | OPIVX | Moves elements up by a scalar amount (vd[i] = vs2[i - rs1]). |
| VSLL.VI | VSLL.VI vd, vs2, imm, vm | OPIVI | Shifts elements left by immediate. |
| VSLL.VV | VSLL.VV vd, vs2, vs1, vm | OPIVV | Shifts elements of vector vs2 left by amounts in vs1. |
| VSM.V | VSM.V vs3, (rs1) | VS-Type | Stores a vector mask register to memory. |
| VSMUL.VV | VSMUL.VV vd, vs2, vs1, vm | OPIVV | Performs signed saturating multiplication, keeping the high half of the product (Fixed-point support). |
| VSOXEI32.V | VSOXEI32.V vs3, (rs1), vs2, vm | VS-Type | Stores elements using indices, ensuring order. |
| VSRA.VI | VSRA.VI vd, vs2, imm, vm | OPIVI | Shifts elements right (arithmetic) by immediate. |
| VSRA.VV | VSRA.VV vd, vs2, vs1, vm | OPIVV | Shifts elements of vector vs2 right (arithmetic) by amounts in vs1. |
| VSRL.VI | VSRL.VI vd, vs2, imm, vm | OPIVI | Shifts elements right (logical) by immediate. |
| VSRL.VV | VSRL.VV vd, vs2, vs1, vm | OPIVV | Shifts elements of vector vs2 right (logical) by amounts in vs1. |
| VSSE32.V | VSSE32.V vs3, (rs1), rs2, vm | VS-Type | Stores elements to memory with a fixed stride. |
| VSSEG2E16.V | VSSEG2E16.V vs3, (rs1), vm | VS-Type | Stores 2 vector registers as interleaved 16-bit fields. |
| VSSEG3E8.V | VSSEG3E8.V vs3, (rs1), vm | VS-Type | Stores 3 vector registers (e.g., RGB) into memory as interleaved 8-bit fields. |
| VSSEG4E8.V | VSSEG4E8.V vs3, (rs1), vm | VS-Type | Stores 4 vector registers (e.g., RGBA) into memory as interleaved 8-bit fields. |
| VSSRA.VV | VSSRA.VV vd, vs2, vs1, vm | OPIVV | Shifts right with sign extension and rounding/saturation logic. |
| VSSRL.VV | VSSRL.VV vd, vs2, vs1, vm | OPIVV | Shifts right with zero extension and rounding/saturation logic. |
| VSSUB.VV | VSSUB.VV vd, vs2, vs1, vm | OPIVV | Subtracts elements with signed saturation. |
| VSSUBU.VV | VSSUBU.VV vd, vs2, vs1, vm | OPIVV | Subtracts unsigned integers with saturation (clips to 0 instead of wrapping). |
| VSUB.VV | VSUB.VV vd, vs2, vs1, vm | OPIVV | Subtracts elements of two vector registers. |
| VSUXEI32.V | VSUXEI32.V vs3, (rs1), vs2, vm | VS-Type | Stores elements to memory using a vector of indices (Scatter). |
| VWADD.VV | VWADD.VV vd, vs2, vs1, vm | OPIVV | Adds N-bit elements to produce 2*N-bit results (Widening). |
| VWADDU.VV | VWADDU.VV vd, vs2, vs1, vm | OPIVV | Adds unsigned N-bit elements to produce unsigned 2*N-bit results. |
| VWMACC.VV | VWMACC.VV vd, vs1, vs2, vm | OPIVV | Computes vd = vd + (vs1 * vs2) with widening (N*N -> 2N + 2N). |
| VWMACCSU.VV | VWMACCSU.VV vd, vs1, vs2, vm | OPIVV | vd = vd + (signed(vs1) * unsigned(vs2)). |
| VWMACCU.VV | VWMACCU.VV vd, vs1, vs2, vm | OPIVV | Computes vd = vd + (vs1 * vs2) widening unsigned. |
| VWMACCUS.VX | VWMACCUS.VX vd, rs1, vs2, vm | OPIVV | vd = vd + (unsigned(vs1) * signed(vs2)). |
| VWMUL.VV | VWMUL.VV vd, vs2, vs1, vm | OPIVV | Multiplies N-bit elements to produce 2*N-bit results. |
| VWREDSUM.VS | VWREDSUM.VS vd, vs2, vs1, vm | OPMVV | Sums N-bit elements into a 2*N-bit scalar accumulator (Signed). |
| VWREDSUMU.VS | VWREDSUMU.VS vd, vs2, vs1, vm | OPMVV | Sums N-bit elements into a 2*N-bit scalar accumulator (Unsigned). |
| VWSUB.VV | VWSUB.VV vd, vs2, vs1, vm | OPIVV | Subtracts N-bit elements to produce 2*N-bit results. |
| VXOR.VI | VXOR.VI vd, vs2, imm, vm | OPIVI | Bitwise XOR with immediate. |
| VXOR.VV | VXOR.VV vd, vs2, vs1, vm | OPIVV | Performs bitwise XOR on elements of two vectors. |