fminnmv
FMINNMV <V><d>, <Pg>, <Zn>.<T>
Floating-point MinNum Reduction.
Pseudocode Operation
No pseudocode available.
Encoding
Binary Layout
01100101
31:24
size
23:22
000
21:19
10
18:17
1
16
001
15:13
Pg
12:10
Zn
9:5
Vd
4:0
Related
More in SVE
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0EB0C800 | FMINNMV <V><d>, <Vn>.<T> | A64 | 0 | Q | 0 | 01110 | 1 | 011000 | 01100 | 10 | Rn | Rd | ||
| 0x6EB0C800 | FMINNMV S<d>, <Vn>.4S | A64 | 0 | 1 | 1 | 01110 | 1 | 0 | 11000 | 01100 | 10 | Rn | Rd | ||
| 0x65052000 | FMINNMV <V><d>, <Pg>, <Zn>.<T> | A64 | 01100101 | size | 000 | 10 | 1 | 001 | Pg | Zn | Vd |
Description
Floating-point minimum number horizontally over all lanes of a vector using a recursive pairwise reduction, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as the default NaN. Regardless of the value of FPCR.AH, the behavior is as follows:
Operation
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; bits(PL) mask = P[g, PL]; bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL); bits(esize) identity = FPDefaultNaN(FPCR, esize); V[d, esize] = FPReducePredicated(ReduceOp_FMINNUM, operand, mask, identity, FPCR);