faddp

FADDP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Floating-point Add Pairwise.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
01100100
31:24
size
23:22
010
21:19
00
18:17
0
16
100
15:13
Pg
12:10
Zm
9:5
Zdn
4:0
 
Format SVE2
Opcode 0x64108000
Extension SVE2

Related

Other forms of faddp

  • faddp Vector Floating-Point Add Pairwise

More in SVE2

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5E30D800 FADDP H<d>, <Vn>.2H A64 01 | 0 | 111100 | 0 | 11000 | 01101 | 10 | Rn | Rd
0x7E30D800 FADDP <V><d>, <Vn>.<T> A64 01 | 1 | 111100 | sz | 11000 | 01101 | 10 | Rn | Rd
0x2E401400 FADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | 0 | 10 | Rm | 00 | 010 | 1 | Rn | Rd
0x2E20D400 FADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 011100 | sz | 1 | Rm | 11010 | 1 | Rn | Rd
0x64108000 FADDP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01100100 | size | 010 | 00 | 0 | 100 | Pg | Zm | Zdn

Description

Add pairs of adjacent floating-point elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result = Z[dn, VL];
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        if IsEven(e) then
            element1 = Elem[operand1, e + 0, esize];
            element2 = Elem[operand1, e + 1, esize];
        else
            element1 = Elem[operand2, e - 1, esize];
            element2 = Elem[operand2, e + 0, esize];
        Elem[result, e, esize] = FPAdd(element1, element2, FPCR);

Z[dn, VL] = result;