fadda

FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T>

Floating-point Add Across Vector.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout

01100101

31:24

size

23:22

0110

21:18

001

15:13

12:10

9:5

Vdn

4:0

Format SVE

Opcode 0x65182000

Extension SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x65182000	FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T>		A64		01100101 \| size \| 0110 \| 0 \| 0 \| 001 \| Pg \| Zm \| Vdn

Description

Floating-point add a SIMD&FP scalar source and all active lanes of the vector source and place the result destructively in the SIMD&FP scalar source register. Vector elements are processed strictly in order from low to high, with the scalar source providing the initial value. Inactive elements in the source vector are ignored. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Operation

CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(esize) operand1 = V[dn, esize];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(esize) result = operand1;

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element = Elem[operand2, e, esize];
        result = FPAdd(result, element, FPCR);

V[dn, esize] = result;