fclamp

Floating-Point Clamp

FCLAMP <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

Clamps floating-point elements between min and max (SVE2.1).

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout

01100100

31:24

size

23:22

20:16

001001

15:10

9:5

4:0

Format SVE2.1

Opcode 0x64202400

Extension SVE2p1

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0xC120C000	FCLAMP { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<T>, <Zm>.<T>	A64	11000001 \| size \| 1 \| Zm \| 110000 \| Zn \| Zd \| 0
0xC120C800	FCLAMP { <Zd1>.<T>-<Zd4>.<T> }, <Zn>.<T>, <Zm>.<T>	A64	11000001 \| size \| 1 \| Zm \| 110010 \| Zn \| Zd \| 0 \| 0
0x64202400	FCLAMP <Zd>.<T>, <Zn>.<T>, <Zm>.<T>	A64	01100100 \| size \| 1 \| Zm \| 001001 \| Zn \| Zd

Description

Clamp each floating-point element in the destination vector to between the floating-point minimum value in the corresponding element of the first source vector and the floating-point maximum value in the corresponding element of the second source vector and destructively place the clamped results in the corresponding elements of the destination vector. Regardless of the value of FPCR.AH, the behavior is as follows for each minimum number and maximum number operation: This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(VL) result;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) operand3 = Z[d, VL];

for e = 0 to elements-1
    bits(esize) element1 = Elem[operand1, e, esize];
    bits(esize) element2 = Elem[operand2, e, esize];
    bits(esize) element3 = Elem[operand3, e, esize];
    Elem[result, e, esize] = FPMinNum(FPMaxNum(element1, element3, FPCR), element2, FPCR);
Z[d, VL] = result;