fcvt
FCVT <Zd>.D, <Pg>/M, <Zn>.S
Floating-point Convert Precision.
Pseudocode Operation
No pseudocode available.
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x1EE24000 | FCVT <Sd>, <Hn> | A64 | 0 | 0 | 0 | 11110 | 11 | 10001 | 00 | 10000 | Rn | Rd | ||
| 0x1EE2C000 | FCVT <Dd>, <Hn> | A64 | 0 | 0 | 0 | 11110 | 11 | 10001 | 01 | 10000 | Rn | Rd | ||
| 0x1E23C000 | FCVT <Hd>, <Sn> | A64 | 0 | 0 | 0 | 11110 | 00 | 10001 | 11 | 10000 | Rn | Rd | ||
| 0x1E22C000 | FCVT <Dd>, <Sn> | A64 | 0 | 0 | 0 | 11110 | 00 | 10001 | 01 | 10000 | Rn | Rd | ||
| 0x1E63C000 | FCVT <Hd>, <Dn> | A64 | 0 | 0 | 0 | 11110 | 01 | 10001 | 11 | 10000 | Rn | Rd | ||
| 0x1E624000 | FCVT <Sd>, <Dn> | A64 | 0 | 0 | 0 | 11110 | 01 | 10001 | 00 | 10000 | Rn | Rd | ||
| 0xC1A0E000 | FCVT { <Zd1>.S-<Zd2>.S }, <Zn>.H | A64 | 1100000110100000111000 | Zn | Zd | 0 | ||
| 0xC124E000 | FCVT <Zd>.B, { <Zn1>.H-<Zn2>.H } | A64 | 110000010 | 0 | 100100111000 | Zn | 0 | Zd | ||
| 0xC134E000 | FCVT <Zd>.B, { <Zn1>.S-<Zn4>.S } | A64 | 1100000100110100111000 | Zn | 0 | 0 | Zd | ||
| 0xC120E000 | FCVT <Zd>.H, { <Zn1>.S-<Zn2>.S } | A64 | 110000010 | 0 | 100000111000 | Zn | 0 | Zd | ||
| 0x6589A000 | FCVT <Zd>.S, <Pg>/M, <Zn>.H | A64 | 01100101 | 1 | 0 | 0010 | 0 | 1 | 101 | Pg | Zn | Zd | ||
| 0x65C9A000 | FCVT <Zd>.D, <Pg>/M, <Zn>.H | A64 | 01100101 | 1 | 1 | 0010 | 0 | 1 | 101 | Pg | Zn | Zd | ||
| 0x6588A000 | FCVT <Zd>.H, <Pg>/M, <Zn>.S | A64 | 01100101 | 1 | 0 | 0010 | 0 | 0 | 101 | Pg | Zn | Zd | ||
| 0x65CBA000 | FCVT <Zd>.D, <Pg>/M, <Zn>.S | A64 | 01100101 | 1 | 1 | 0010 | 1 | 1 | 101 | Pg | Zn | Zd |
Description
Convert the size and precision of each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified. Since the input and result types have a different size the smaller type is held unpacked in the least significant bits of elements of the larger size. When the input is the smaller type the upper bits of each source element are ignored. When the result is the smaller type the results are zero-extended to fill each destination element.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];
for e = 0 to elements-1
if ActivePredicateElement(mask, e, esize) then
bits(esize) element = Elem[operand, e, esize];
bits(d_esize) res = FPConvertSVE(element<s_esize-1:0>, FPCR, d_esize);
Elem[result, e, esize] = ZeroExtend(res, esize);
Z[d, VL] = result;