cnot

CNOT <Zd>.<T>, <Pg>/M, <Zn>.<T>

Logical Negate (Condition)

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout

00000100

31:24

size

23:22

011

21:19

18:17

101

15:13

12:10

9:5

4:0

Format SVE

Opcode 0x041BA000

Extension SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x041BA000	CNOT <Zd>.<T>, <Pg>/M, <Zn>.<T>		A64		00000100 \| size \| 011 \| 01 \| 1 \| 101 \| Pg \| Zn \| Zd

Description

Logically invert the boolean value in each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified. Boolean TRUE is any non-zero value in a source, and one in a result element. Boolean FALSE is always zero.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element = Elem[operand, e, esize];
        Elem[result, e, esize] = ZeroExtend(IsZeroBit(element), esize);

Z[d, VL] = result;