bsl

Bitwise Select (SVE2)

BSL <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D

Bitwise select using (Zdn AND Zm) OR (NOT Zdn AND Zk).

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout

00000100

31:24

20:16

00111

15:11

9:5

Zdn

4:0

Format SVE2 Bitwise

Opcode 0x04203C00

Extension SVE2

Operands

Zdn
Dest/Mask
Zm
True
Zk
False

Other forms of bsl

bsl Bitwise Select

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x2E601C00	BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>		A64		0 \| Q \| 1 \| 01110 \| 01 \| 1 \| Rm \| 00011 \| 1 \| Rn \| Rd
0x04203C00	BSL <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D		A64		00000100 \| 0 \| 0 \| 1 \| Zm \| 00111 \| 1 \| Zk \| Zdn

Description

Selects bits from the first source vector where the corresponding bit in the third source vector is '1', and from the second source vector where the corresponding bit in the third source vector is '0'. The result is placed destructively in the destination and first source vector. This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) operand3 = Z[k, VL];

Z[dn, VL] = (operand1 AND operand3) OR (operand2 AND NOT(operand3));

bsl