bcax

Bitwise Clear and Exclusive OR (SVE2)

BCAX <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D

Calculates (Zn AND NOT Zm) XOR Zk.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
00000100
31:24
0
23
1
22
1
21
Zm
20:16
00111
15:11
0
10
Zk
9:5
Zdn
4:0
 
Format SVE2 Bitwise
Opcode 0x04603800
Extension SVE2

Operands

  • Zdn
    Dest
  • Zm
    Src 2
  • Zk
    Src 3

Related

More in SVE2

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0xCE200000 BCAX <Vd>.16B, <Vn>.16B, <Vm>.16B, <Va>.16B A64 110011100 | 01 | Rm | 0 | Ra | Rn | Rd
0x04603800 BCAX <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D A64 00000100 | 0 | 1 | 1 | Zm | 00111 | 0 | Zk | Zdn

Description

Bitwise AND elements of the second source vector with the corresponding inverted elements of the third source vector, then exclusive OR the results with corresponding elements of the first source vector. The final results are destructively placed in the corresponding elements of the destination and first source vector. This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) operand3 = Z[k, VL];

Z[dn, VL] = operand1 EOR (operand2 AND NOT(operand3));