ands
ANDS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
Predicate AND (Set Flags)
Pseudocode Operation
No pseudocode available.
Encoding
Binary Layout
00100101
31:24
0
23
1
22
00
21:20
Pm
19:16
01
15:14
Pg
13:10
0
9
Pn
8:5
0
4
Pd
3:0
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x72000000 | ANDS <Wd>, <Wn>, #<imm> | A64 | 0 | 11 | 100100 | 0 | immr | imms | Rn | Rd | ||
| 0xF2000000 | ANDS <Xd>, <Xn>, #<imm> | A64 | 1 | 11 | 100100 | N | immr | imms | Rn | Rd | ||
| 0x6A000000 | ANDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>} | A64 | 0 | 11 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd | ||
| 0xEA000000 | ANDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>} | A64 | 1 | 11 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd | ||
| 0x25404000 | ANDS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B | A64 | 00100101 | 0 | 1 | 00 | Pm | 01 | Pg | 0 | Pn | 0 | Pd |
Description
Bitwise AND active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(PL) operand1 = P[n, PL];
bits(PL) operand2 = P[m, PL];
bits(PL) result;
constant integer psize = esize DIV 8;
for e = 0 to elements-1
bit element1 = PredicateElement(operand1, e, esize);
bit element2 = PredicateElement(operand2, e, esize);
if ActivePredicateElement(mask, e, esize) then
Elem[result, e, psize] = ZeroExtend(element1 AND element2, psize);
else
Elem[result, e, psize] = ZeroExtend('0', psize);
if setflags then
PSTATE.<N,Z,C,V> = PredTest(mask, result, esize);
P[d, PL] = result;