bext

Bit Extract (SVE2)

BEXT <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

Extracts bits from source to destination based on a mask (Gather bits).

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout

01000101

31:24

size

23:22

20:16

1011

15:12

9:5

4:0

Format SVE2 Bitwise

Opcode 0x4500B000

Extension SVE2

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x4500B000	BEXT <Zd>.<T>, <Zn>.<T>, <Zm>.<T>		A64		01000101 \| size \| 0 \| Zm \| 1011 \| 0 \| 0 \| Zn \| Zd

Description

This instruction gathers bits in each element of the first source vector from the bit positions indicated by non-zero bits in the corresponding mask element of the second source vector to the lowest-numbered contiguous bits of the corresponding destination element, preserving their order, and sets the remaining higher-numbered bits to zero. This instruction is unpredicated. ID_AA64ZFR0_EL1.BitPerm indicates whether this instruction is implemented. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Operation

CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
bits(VL) data = Z[n, VL];
bits(VL) mask = Z[m, VL];
bits(VL) result;

for e = 0 to elements - 1
    Elem[result, e, esize] = BitExtract(Elem[data, e, esize], Elem[mask, e, esize]);

Z[d, VL] = result;