aesmc
AESMC <Zdn>.B, <Zdn>.B
AES Mix Columns.
Pseudocode Operation
No pseudocode available.
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x4E286800 | AESMC <Vd>.16B, <Vn>.16B | A64 | 01001110 | 00 | 101000011 | 0 | 10 | Rn | Rd | ||
| 0x4520E000 | AESMC <Zdn>.B, <Zdn>.B | A64 | 01000101 | 0 | 0 | 10000011100 | 0 | 00000 | Zdn |
Description
The AESMC instruction reads a 16-byte state array from each 128-bit segment of the source register, and performs a single round of the MixColumns() transformation on each state array in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. This instruction is unpredicated. ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
Operation
CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer segments = VL DIV 128;
bits(VL) operand = Z[dn, VL];
bits(VL) result;
for s = 0 to segments-1
Elem[result, s, 128] = AESMixColumns(Elem[operand, s, 128]);
Z[dn, VL] = result;