cmpge
CMPGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
Integer Compare Greater Equal.
Pseudocode Operation
No pseudocode available.
Encoding
Binary Layout
00100100
31:24
size
23:22
0
21
Zm
20:16
1
15
0
14
0
13
Pg
12:10
Zn
9:5
0
4
Pd
3:0
Related
More in SVE
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x25000000 | CMPGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm> | A64 | 00100101 | size | 0 | imm5 | 0 | 0 | 0 | Pg | Zn | 0 | Pd | ||
| 0x24004000 | CMPGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D | A64 | 00100100 | size | 0 | Zm | 0 | 1 | 0 | Pg | Zn | 0 | Pd | ||
| 0x24008000 | CMPGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> | A64 | 00100100 | size | 0 | Zm | 1 | 0 | 0 | Pg | Zn | 0 | Pd |
Description
Compare active integer elements in the first source vector with corresponding elements in the second source vector, and place the boolean results of the specified comparison in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(PL) result;
constant integer psize = esize DIV 8;
for e = 0 to elements-1
integer element1 = Int(Elem[operand1, e, esize], unsigned);
if ActivePredicateElement(mask, e, esize) then
boolean cond;
integer element2 = Int(Elem[operand2, e, esize], unsigned);
case op of
when Cmp_EQ cond = element1 == element2;
when Cmp_NE cond = element1 != element2;
when Cmp_GE cond = element1 >= element2;
when Cmp_LT cond = element1 < element2;
when Cmp_GT cond = element1 > element2;
when Cmp_LE cond = element1 <= element2;
bit pbit = if cond then '1' else '0';
Elem[result, e, psize] = ZeroExtend(pbit, psize);
else
Elem[result, e, psize] = ZeroExtend('0', psize);
PSTATE.<N,Z,C,V> = PredTest(mask, result, esize);
P[d, PL] = result;