bsl2n

Bitwise Select 2 NOT (SVE2)

BSL2N <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D

Bitwise select with second operand inverted.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
00000100
31:24
1
23
0
22
1
21
Zm
20:16
00111
15:11
1
10
Zk
9:5
Zdn
4:0
 
Format SVE2 Bitwise
Opcode 0x04A03C00
Extension SVE2

Operands

  • Zdn
    Dest
  • Zm
    Src 2
  • Zk
    Src 3

Related

More in SVE2

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x04A03C00 BSL2N <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D A64 00000100 | 1 | 0 | 1 | Zm | 00111 | 1 | Zk | Zdn

Description

Selects bits from the first source vector where the corresponding bit in the third source vector is '1', and from the inverted second source vector where the corresponding bit in the third source vector is '0'. The result is placed destructively in the destination and first source vector. This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) operand3 = Z[k, VL];

Z[dn, VL] = (operand1 AND operand3) OR (NOT(operand2) AND NOT(operand3));