asrd

ASRD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>

Arithmetic Shift Right for Divide.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout

00000100

31:24

tszh

23:22

21:20

100

15:13

12:10

tszl

9:8

imm3

7:5

Zdn

4:0

Format SVE

Opcode 0x04048000

Extension SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x04048000	ASRD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>		A64		00000100 \| tszh \| 00 \| 0 \| 1 \| 0 \| 0 \| 100 \| Pg \| tszl \| imm3 \| Zdn

Description

Shift right by immediate, preserving the sign bit, each active element of the source vector, and destructively place the results in the corresponding elements of the source vector. The result rounds toward zero as in a signed division. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) result;

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        integer element1 = SInt(Elem[operand1, e, esize]);
        if element1 < 0 then
            element1 = element1 + ((1 << shift) - 1);
        Elem[result, e, esize] = (element1 >> shift)<esize-1:0>;
    else
        Elem[result, e, esize] = Elem[operand1, e, esize];

Z[dn, VL] = result;