frecpx

FRECPX <Zd>.<T>, <Pg>/M, <Zn>.<T>

Floating-point Reciprocal Exponent.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout

01100101

31:24

size

23:22

0011

21:18

101

15:13

12:10

9:5

4:0

Format SVE

Opcode 0x650CA000

Extension SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x5EF9F800	FRECPX <Hd>, <Hn>	A64	01 \| 0 \| 11110 \| 1 \| 111100 \| 11111 \| 10 \| Rn \| Rd
0x5EA1F800	FRECPX <V><d>, <V><n>	A64	01 \| 0 \| 111101 \| sz \| 10000 \| 11111 \| 10 \| Rn \| Rd
0x650CA000	FRECPX <Zd>.<T>, <Pg>/M, <Zn>.<T>	A64	01100101 \| size \| 0011 \| 0 \| 0 \| 101 \| Pg \| Zn \| Zd

Description

Invert the exponent and zero the fractional part of each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified. The result of this instruction can be used with FMULX to convert arbitrary elements in mathematical vector space to "unit vectors" or "direction vectors" of length 1.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element = Elem[operand, e, esize];
        Elem[result, e, esize] = FPRecpX(element, FPCR);

Z[d, VL] = result;