histcnt

SVE Histogram Count

HISTCNT <Zd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>

Counts active elements that match specific bit patterns (Histogram acceleration).

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout

01000101

31:24

size

23:22

20:16

110

15:13

12:10

9:5

4:0

Format SVE2 Histogram

Opcode 0x4520C000

Extension SVE2

Operands

Zd
Dest (Counts)
Pg
Mask
Zn
Input
Zm
Reference

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x4520C000	HISTCNT <Zd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>		A64		01000101 \| size \| 1 \| Zm \| 110 \| Pg \| Zn \| Zd

Description

This instruction compares each active 32 or 64-bit element of the first source vector with all active elements with an element number less than or equal to its own in the second source vector, and places the count of matching elements in the corresponding element of the destination vector. Inactive elements in the destination vector are set to zero. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Operation

CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;

for e = 0 to elements-1
    integer count = 0;
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element1 = Elem[operand1, e, esize];
        for i = 0 to e
            if ActivePredicateElement(mask, i, esize) then
                bits(esize) element2 = Elem[operand2, i, esize];
                if element1 == element2 then
                    count = count + 1;
    Elem[result, e, esize] = count<esize-1:0>;

Z[d, VL] = result;