ld2w
Load 2-element Structure (Word)
Pseudocode Operation
No pseudocode available.
Encoding
Related
More in SVE
Reference
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0xA520E000 | LD2W { <Zt1>.S, <Zt2>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] | A64 | 1010010 | 1 | 0 | 01 | 0 | imm4 | 111 | Pg | Rn | Zt | ||
| 0xA520C000 | LD2W { <Zt1>.S, <Zt2>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2] | A64 | 1010010 | 1 | 0 | 01 | Rm | 110 | Pg | Rn | Zt |
Description
Contiguous load two-word structures, each to the same element number in two vector registers from the memory address generated by a 64-bit scalar base and an immediate index which is a multiple of 2 in the range -16 to 14 that is multiplied by the vector's in-memory size, irrespective of predication, Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive words in memory which make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the two destination vector registers.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(64) base;
bits(PL) mask = P[g, PL];
constant integer mbytes = esize DIV 8;
array [0..1] of bits(VL) values;
boolean contiguous = TRUE;
boolean nontemporal = FALSE;
boolean tagchecked = n != 31;
AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked);
if !AnyActiveElement(mask, esize) then
if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then
CheckSPAlignment();
else
if n == 31 then CheckSPAlignment();
base = if n == 31 then SP[] else X[n, 64];
for e = 0 to elements-1
for r = 0 to nreg-1
if ActivePredicateElement(mask, e, esize) then
integer eoff = (offset * elements * nreg) + (e * nreg) + r;
bits(64) addr = GenerateAddress(base, eoff * mbytes, accdesc);
Elem[values[r], e, esize] = Mem[addr, mbytes, accdesc];
else
Elem[values[r], e, esize] = Zeros(esize);
for r = 0 to nreg-1
Z[(t+r) MOD 32, VL] = values[r];