ldnt1h
LDNT1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
Load Non-Temporal (Half)
Pseudocode Operation
No pseudocode available.
Encoding
Binary Layout
1010010
31:25
0
24
1
23
000
22:20
imm4
19:16
111
15:13
Pg
12:10
Rn
9:5
Zt
4:0
Related
More in SVE2
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0xA0402001 | LDNT1H { <Zt1>.H-<Zt2>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] | A64 | 101000000100 | imm4 | 0 | 0 | 1 | PNg | Rn | Zt | 1 | ||
| 0xA040A001 | LDNT1H { <Zt1>.H-<Zt4>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] | A64 | 101000000100 | imm4 | 1 | 0 | 1 | PNg | Rn | Zt | 0 | 1 | ||
| 0xA0002001 | LDNT1H { <Zt1>.H-<Zt2>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1] | A64 | 10100000000 | Rm | 0 | 0 | 1 | PNg | Rn | Zt | 1 | ||
| 0xA000A001 | LDNT1H { <Zt1>.H-<Zt4>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1] | A64 | 10100000000 | Rm | 1 | 0 | 1 | PNg | Rn | Zt | 0 | 1 | ||
| 0xA1402008 | LDNT1H { <Zt1>.H, <Zt2>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] | A64 | 101000010100 | imm4 | 0 | 0 | 1 | PNg | Rn | T | 1 | Zt | ||
| 0xA140A008 | LDNT1H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] | A64 | 101000010100 | imm4 | 1 | 0 | 1 | PNg | Rn | T | 1 | 0 | Zt | ||
| 0xA1002008 | LDNT1H { <Zt1>.H, <Zt2>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1] | A64 | 10100001000 | Rm | 0 | 0 | 1 | PNg | Rn | T | 1 | Zt | ||
| 0xA100A008 | LDNT1H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #1] | A64 | 10100001000 | Rm | 1 | 0 | 1 | PNg | Rn | T | 1 | 0 | Zt | ||
| 0x8480A000 | LDNT1H { <Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}] | A64 | 1000010 | 0 | 1 | 00 | Rm | 10 | 1 | Pg | Zn | Zt | ||
| 0xC480C000 | LDNT1H { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}] | A64 | 1100010 | 0 | 1 | 00 | Rm | 1 | 1 | 0 | Pg | Zn | Zt | ||
| 0xA480E000 | LDNT1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] | A64 | 1010010 | 0 | 1 | 000 | imm4 | 111 | Pg | Rn | Zt | ||
| 0xA480C000 | LDNT1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1] | A64 | 1010010 | 0 | 1 | 00 | Rm | 110 | Pg | Rn | Zt |
Description
Contiguous load non-temporal of halfwords to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(64) base;
bits(PL) mask = P[g, PL];
bits(VL) result;
constant integer mbytes = esize DIV 8;
boolean contiguous = TRUE;
boolean nontemporal = TRUE;
boolean tagchecked = n != 31;
AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked);
if !AnyActiveElement(mask, esize) then
if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then
CheckSPAlignment();
else
if n == 31 then CheckSPAlignment();
base = if n == 31 then SP[] else X[n, 64];
for e = 0 to elements-1
if ActivePredicateElement(mask, e, esize) then
integer eoff = (offset * elements) + e;
bits(64) addr = GenerateAddress(base, eoff * mbytes, accdesc);
Elem[result, e, esize] = Mem[addr, mbytes, accdesc];
else
Elem[result, e, esize] = Zeros(esize);
Z[t, VL] = result;