pmullt
SVE Polynomial Multiply Long (Top)
PMULLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
Polynomial multiply of odd elements producing wide result.
Pseudocode Operation
No pseudocode available.
Encoding
Binary Layout
01000101
31:24
size
23:22
0
21
Zm
20:16
011
15:13
0
12
1
11
1
10
Zn
9:5
Zd
4:0
Related
More in SVE2
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x45006C00 | PMULLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb> | A64 | 01000101 | size | 0 | Zm | 011 | 0 | 1 | 1 | Zn | Zd | ||
| 0x45006C00 | PMULLT <Zd>.Q, <Zn>.D, <Zm>.D | A64 | 01000101 | 0 | 0 | 0 | Zm | 011 | 0 | 1 | 1 | Zn | Zd |
Description
Polynomial multiply over [0, 1] the corresponding odd-numbered elements of the first and second source vectors, and place the results in the overlapping double-width elements of the destination vector. This instruction is unpredicated. ID_AA64ZFR0_EL1.AES indicates whether the 128-bit element variant is implemented. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
Operation
if esize < 128 then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) result;
for e = 0 to elements-1
bits(esize DIV 2) element1 = Elem[operand1, 2*e + 1, esize DIV 2];
bits(esize DIV 2) element2 = Elem[operand2, 2*e + 1, esize DIV 2];
Elem[result, e, esize] = PolynomialMult(element1, element2);
Z[d, VL] = result;