rdvl

RDVL <Xd>, #<imm>

Read Vector Length.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
000001001
31:23
0
22
1
21
1111
20:17
1
16
01010
15:11
imm6
10:5
Rd
4:0
 
Format SVE
Opcode 0x04BF5000
Extension SVE

Related

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x04BF5000 RDVL <Xd>, #<imm> A64 000001001 | 0 | 1 | 1111 | 1 | 01010 | imm6 | Rd

Description

Multiply the current vector register size in bytes by an immediate in the range -32 to 31 and place the result in the 64-bit destination general-purpose register.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
integer len = imm * (VL DIV 8);
X[d, 64] = len<63:0>;